Transistors employing a ferroelectric as a gate insulation film are expected to be next-generation highly integrated memories because data storage, data readout, and writing are conducted in the individual transistors. In this kind of transistor, electrical conduction in the transistor is controlled according to the direction of electric polarization of the ferroelectric. Virtually, structures comprising an insulator buffer layer inserted between a semiconductor and a ferroelectric so as not to impair the features of both of the semiconductor and the ferroelectric have been investigated (see, for example, patent documents 1 and 2). Transistors of this structure including the metal gate electrode in contact with the ferroelectric are called MFIS (Metal-Ferroelectrics-Insulator-Semiconductor) transistors.
In principle, the MFIS transistors are expected to have the following features: (1) no data disappear even when the power is turned off, because electric polarization is utilized; (2) the only thing necessary for a readout operation is to check the electrical conduction between the source and the drain in the transistor, and the contents of the data remain undestroyed even after the readout operation; and (3) the speed of data readout and writing are as high as that of DRAMs.
However, the MFIS transistors heretofore have had a problem that after data writing, the data disappear in terms of memory transistor operation in about 1 day at most (see, for example, non-patent documents 1 and 2).    Patent Document 1: JP-A-2001-291841    Patent Document 2: JP-A-2002-353420    Non-Patent Document 1: S. Migita et al., Integrated Ferroelectrics, Vol. 40, pp. 135–143, 2001    Non-Patent Document 2: Shinji Migita et al., Denshi Jôhô Tsûshin Gakkai Ronbun-shi, Vol. J85-C, No. 1 (January 2002 issue), pp. 14–22